🚀 We''re Hiring: Senior Physical Design (PD) Engineer

📍 Location: Bay Area, CA (Onsite)
💼 Experience: 8+ Years

Sivaltech is looking for an experienced Senior Physical Design (PD) Engineer to join our semiconductor team. If you have expertise in advanced-node ASIC physical design and are passionate about delivering high-quality silicon, we''d love to connect with you!

Key Responsibilities

• Perform end-to-end ASIC physical design implementation from netlist to GDSII.

• Drive Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, and Physical Optimization.

• Perform Static Timing Analysis (STA) and timing closure.

• Resolve setup/hold violations, signal integrity, IR drop, and EM issues.

• Execute physical verification (DRC/LVS) and ECO implementation.

• Collaborate with RTL, Design Verification, DFT, and STA teams to achieve successful tape-outs.

• Support advanced technology nodes and multiple ASIC tape-outs.

Required Skills

• 8+ years of ASIC Physical Design experience.

• Strong expertise in:

  • Floorplanning

  • Placement

  • CTS

  • Routing

  • Physical Implementation

  • Timing Closure

  • STA

  • Physical Verification

• Hands-on experience with industry-standard EDA tools such as:

  • Synopsys ICC2 / Fusion Compiler / PrimeTime

  • Cadence Innovus / Tempus

  • Calibre

• Strong scripting skills in Tcl, Perl, Python, or Shell.

• Experience with advanced process nodes (7nm, 5nm, 3nm, or below) is preferred.

Why Join Us?

• Work on cutting-edge semiconductor technologies.

• Collaborate with experienced engineering teams.

• Contribute to innovative ASIC and SoC development programs.

📩 Interested? Please share your resume or reach out to discuss this opportunity.

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