Physical Design Engineer & DV Engineers

Job Summary
Seeking a Physical Design Engineer with strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoC designs.
Key Responsibilities
• Perform block-level and top-level Physical Design implementation using Fusion Compiler.
• Drive floorplanning, placement, CTS, routing, and timing closure.
• Execute and analyze Static Timing Analysis (STA) across multiple corners and modes.
• Implement and verify low-power designs using UPF, including isolation, level shifters, retention, and power domain checks.
• Support physical signoff activities such as DRC, LVS, IR drop, and EM analysis.
• Collaborate with RTL, DFT, Power, and Signoff teams to achieve PPA targets.
Required Qualifications
• Bachelor''s or Master''s degree in Electrical Engineering, Computer Engineering, or related field.
• Strong experience in Physical Design and PnR flows.
• Hands-on expertise with Synopsys Fusion Compiler.
• Solid understanding of STA, timing closure, and MMMC methodologies.
• Experience with low-power implementation and verification flows.
• Good scripting skills in Tcl, Perl, or Python.
Preferred
• Experience with advanced technology nodes (7nm and below).
• Exposure to full-chip integration and signoff methodologies.
• Strong debugging and problem-solving skills.