Layout Design Engineer with SRAM Experience

Sr. Layout Design Engineer with SRAM Experience

Location : Santa Clara, CA

Location : Remote

 

· 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.

· Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.

· Solid grasp of SRAM and memory layout principles.

· Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.

· Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.

· Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.

 

 

 “Tekshapers is an equal opportunity employer and will consider all applications without regards to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.”