Signal Integrity Engineer

Hyve Company Overview

Hyve Solutions transforms complex engineering challenges into production reality for technology innovators building AI, cloud, and connected infrastructure. As a US-based manufacturing partner, the company rapidly delivers fast, agile execution through dep technical partnerships and co-innovation, and supply chain clarity. Hyve's integrated ODM, CM, and SI capabilities eliminate vendor complexity while accelerating time-to-market with single-partner accountability from design through scale. The company co-innovates with deep engineering expertise, treating customer success as its own while building tomorrow's digital infrastructure.

Key Responsibilities
Signal Integrity Analysis

• Perform pre-layout and post-layout signal integrity simulations for high-speed interfaces including PCIe, CXL, Ethernet, SerDes, and DDR5/DDR6 technologies under the guidance of senior SI/PI engineers.
• Analyze channel performance, insertion loss, return loss, crosstalk, and timing margins to support robust platform design.
• Evaluate design tradeoffs and provide recommendations to improve signal quality and overall system performance.

Modeling & Simulation

• Develop and execute channel models using industry-standard tools such as HFSS, ADS, HSPICE, Sigrity, or comparable simulation environments.
• Support stackup development, impedance control requirements, and routing rule definition for high-speed PCB designs.
• Assist with connector, cable, package, and channel characterization activities.

Lab Validation & Correlation

• Support signal integrity validation using high-speed oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), and Bit Error Rate Testers (BERT).
• Correlate simulation results with laboratory measurements and identify opportunities for model refinement.
• Assist with compliance testing and validation for industry-standard interfaces.

Design & Platform Support

• Collaborate with hardware design and PCB layout engineers to ensure adherence to SI best practices and design guidelines.
• Provide technical support for routing strategies, connector selection, cable design, and high-speed channel optimization.
• Participate in EVT, DVT, and PVT bring-up activities and support debug efforts for signal integrity-related issues.

Documentation & Reporting

• Maintain simulation reports, measurement results, compliance documentation, and engineering recommendations.
• Document methodologies, findings, and corrective actions to support design reviews and product releases.
• Contribute to the development of SI design guidelines and best practices.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering or a related technical discipline.
• 2-5 years of experience in Signal Integrity, High-Speed Digital Design, Hardware Engineering, or related disciplines.
• Internship, co-op, academic research, or project experience involving channel simulation, high-speed interfaces, or laboratory measurements is highly desirable.
• Working knowledge of transmission line theory, electromagnetic fundamentals, PCB stackups, and high-speed channel design.
• Familiarity with SI simulation and modeling tools such as HFSS, ADS, HSPICE, Sigrity, CST, or equivalent.
• Experience working with laboratory equipment including oscilloscopes, VNAs, TDRs, and related measurement tools.
• Understanding of impedance control, crosstalk, jitter, eye diagram analysis, and channel loss mechanisms.
• Strong analytical, troubleshooting, and problem-solving skills.
• Excellent written and verbal communication skills with the ability to present technical findings clearly.
• Demonstrated attention to detail and ability to work effectively in cross-functional engineering environments.

Preferred Qualifications

• Experience supporting AI, GPU, server, storage, networking, or data center hardware platforms.
• Familiarity with PCIe Gen4/5/6, CXL, DDR5/DDR6, Ethernet, SerDes, and related industry standards.
• Knowledge of Intel and/or AMD server architectures.
• Experience supporting EVT, DVT, and PVT development cycles.
• Understanding of package, board, connector, and cable interactions in high-speed systems.
• Exposure to compliance testing methodologies and industry certification requirements.
• Experience collaborating with SI, PI, hardware design, layout, mechanical, and manufacturing engineering teams.
• Familiarity with power integrity concepts and their interaction with signal integrity performance.

Compensation & Benefits

• Competitive salary commensurate with experience and qualifications.
• Comprehensive medical, dental, and vision insurance.
• 401(k) with company match.
• Flexible Spending Account (FSA).
• Health Savings Account (HSA).
• Paid holidays, vacation, and sick time.
• Tuition reimbursement programs.
• Professional development and training opportunities.
• Employee discount programs through Perks at Work.
• LEAP career development program.
• MyFlexPay benefit program.

Work Environment

This position operates in a hybrid office and laboratory environment and requires hands-on interaction with development hardware, validation platforms, and advanced test equipment. The role includes extensive collaboration with hardware design, layout, power integrity, and validation teams. Occasional travel may be required to manufacturing facilities, suppliers, customer locations, or engineering laboratories. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions of the role.

Compensation: $99K to $130K

What's in it for you

Benefit Insurance

• Flexible Spending Account (FSA)

• Health Savings Account (HSA)

• Mental Health Care

• 401K with match

• Paid Holidays, Vacation & Sick Days

• Tuition Reimbursement

• Perks at Work

• LEAP Program

• MyFlexPay

We are an Equal Opportunity Employer and do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability, or any other legally protected status. We are committed to creating an inclusive environment for all employees.