Front End Physical Design Engineer at Sunnyvale, CA

Introduction

This position is for a Front End Physical Design Engineer based in Sunnyvale, CA. The successful candidate will be responsible for driving RTL synthesis and optimization to achieve performance, power, and area goals for complex ASIC/SoC designs. They will work closely with various teams to ensure optimal timing, congestion, and power distribution in the design.

Responsibilities

• Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals
• Perform floorplanning for complex ASIC/SoC designs while ensuring optimal timing, congestion, and power distribution
• Collaborate closely with RTL design engineers to provide actionable feedback that improves RTL quality, synthesis results, and overall implementation
• Analyze netlists and identify opportunities for optimization to improve design quality and implementation efficiency
• Work cross-functionally with architecture, RTL, verification, and physical design teams to ensure smooth design convergence
• Support timing closure by identifying implementation bottlenecks and recommending design improvements
• Participate in design reviews and contribute to continuous process and methodology improvements

Requirements

Required Qualifications

• Bachelor''s or Master''s degree in Electrical Engineering, Computer Engineering, or a related field experience
• Strong hands-on experience in ASIC/SoC physical design with 10+ years of industry experience
• Expertise in RTL synthesis and timing optimization
• Solid experience with floorplanning for advanced technology nodes
• Strong understanding of netlist optimization and physical implementation methodologies
• Experience collaborating with RTL/design teams to improve design quality and implementation efficiency
• Excellent communication and cross-functional collaboration skills

Preferred Skills

• Experience with industry-standard EDA tools for synthesis and physical design
• Strong understanding of timing, congestion, power, and area optimization techniques
• Experience working on high-performance CPU, GPU, AI/ML, or networking SoCs is a plus