RTL Engineer – Networking ASIC

Saratoga, CA
Full-Time

Join an innovative hardware company building next-generation Networking ASICs that power large-scale AI training and inference.

We are seeking experienced RTL Engineers to architect and implement high-performance networking chips focused on low latency, QoS, and scalability.

Responsibilities

• Design packet buffering, queuing, and scheduling microarchitecture

• Implement high-speed networking ASIC RTL (SystemVerilog/Verilog)

• Optimize pipelined architectures for performance and latency

• Support Ethernet, IP protocols, and high-speed interconnects (e.g., UCIe)

• Collaborate with verification teams for testing and validation

Qualifications

• BE/ME with 8–15 years of ASIC RTL design experience

• Strong expertise in SystemVerilog & Verilog

• Experience with scheduling, arbitration & QoS mechanisms

• Solid understanding of ASIC design flow (simulation, synthesis, timing)

• Background in Ethernet and IP networking protocols

If you’re passionate about building high-speed networking silicon for AI infrastructure, apply today.