Physical Design with - Genus & Innovus || FTE/W2 || California - onsite

Hi,
Please check the below position Job Title: Physical Design (PD) Engineer Genus & Innovus
Location: California (Onsite/Hybrid)
Employment Type: W2 / Full-Time
Any visa

Job Description
We are seeking an experienced Physical Design (PD) Engineer with 6+ years of ASIC Physical Design experience. The ideal candidate should have strong expertise in Cadence Genus and Innovus and hands-on experience in the complete physical design flow from synthesis through signoff. The candidate will work closely with RTL, DFT, STA, and backend teams to deliver high-performance, low-power, and timing-closed designs. Key Responsibilities

• Execute end-to-end ASIC Physical Design flow including synthesis, floorplanning, placement, CTS, routing, optimization, and physical verification.
• Perform RTL-to-GDSII implementation using Cadence Genus and Cadence Innovus.
• Develop and optimize floorplans considering power, performance, and area (PPA).
• Perform placement optimization, clock tree synthesis (CTS), routing, and congestion analysis.
• Close timing by resolving setup, hold, transition, and capacitance violations.
• Perform power optimization and IR drop analysis.
• Collaborate with RTL, DFT, STA, and verification teams to resolve implementation issues.
• Conduct physical verification including DRC, LVS, and antenna checks.
• Analyze and resolve signal integrity, electromigration (EM), and reliability issues.
• Support ECO implementation and timing closure activities.
• Develop and maintain backend automation scripts using Tcl, Perl, or Python.
• Participate in design reviews and contribute to methodology improvements.

Required Skills

• 6+ years of experience in ASIC Physical Design.
• Strong hands-on experience with Cadence Genus and Cadence Innovus.
• Solid understanding of the complete ASIC implementation flow.
• Experience with floorplanning, placement, CTS, routing, timing closure, and ECO implementation.
• Strong knowledge of Static Timing Analysis (STA) concepts.
• Experience with timing constraints (SDC), MMMC setup, and timing optimization.
• Understanding of physical verification (DRC/LVS) and signoff methodologies.
• Familiarity with low-power design techniques and UPF/CPF.
• Experience with IR drop, EM, signal integrity, and power analysis.
• Proficiency in Linux/Unix environments.
• Strong scripting skills in Tcl, Perl, or Python.
• Excellent debugging, analytical, and problem-solving skills.

Required Tools & Technologies

• Cadence Genus
• Cadence Innovus
• PrimeTime
• Tempus
• Calibre
• Voltus
• RedHawk
• Tcl
• Perl
• Python
• Linux/Unix
• Git