Design Verification Engineer

Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models

• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
• Participate in the validation of ASIC implementations in Verilog/SystemVerilog
• Run formal verification of complex blocks to ensure functional correctness
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C
• Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database
  
  

Export Control Requirement


Basic Qualifications

• Bachelor's degree in Electrical Engineering or a related field
• 5+ years in verification preferably in communication systems
• 2+ years in UVM, C, and scripting
  
  

Preferred Qualifications

• Master's degree in Electrical or Communications Engineering or a related field
• 7+ years in digital verification, preferably in communication systems
• Familiarity with Matlab
• Modem design verification experience
• System C or Matlab model : development or DV integration experience
• Familiarity with formal verification techniques
• Strong written and verbal skills