Senior Semiconductor Layout Engineer (Hybrid in San Jose, CA ) Local only

Senior Semiconductor Layout Engineer

Position Overview

We are seeking an experienced Senior Semiconductor Layout Engineer to develop advanced SRAM and memory IP for next-generation semiconductor technologies. This role focuses on custom IC layout, memory floorplanning, physical verification, and tapeout while working closely with circuit design, physical design, CAD, and process engineering teams.

Responsibilities

Design and optimize custom layouts for SRAM and memory macros, including floorplanning, routing, power distribution, pin planning, and macro integration.

Translate schematics into high-quality physical layouts optimized for performance, area, reliability, and manufacturability.

Perform physical verification including DRC, LVS, ERC, antenna checks, and support successful tapeout.

Address advanced-node requirements including EM/IR, matching, shielding, density, dummy fill, LDE, and DFM.

Collaborate with circuit, physical design, CAD, and foundry teams to resolve layout and integration challenges.

Participate in design reviews, improve layout methodologies, and mentor junior engineers.

Required

Bachelor's degree in Electrical Engineering or equivalent experience.

10+ years of custom IC layout experience, including 5+ years designing SRAM, memory compiler, or custom memory IP.

Strong experience with advanced CMOS technologies (FinFET, GAA, 5nm, 3nm or smaller).

Expert proficiency with Cadence Virtuoso.

Hands-on experience with Calibre, ICV, or similar tools for DRC, LVS, ERC, and physical verification.

Experience with floorplanning, macro integration, routing, top-level verification, and advanced-node layout techniques.

Strong communication and problem-solving skills.