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Senior Principal C++ Software Engineer
Cadence Design Systems IncSan Jose, CA🇺🇸United StatesPosted 14 Aug 2026
Quick Overview
Salary
$154k - $286k/yr
Work Type
Hybrid
Level
Leader
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for an experienced C++ software engineer to join the Protium Software Development Team to develop and enhance the FPGA-Based Prototyping product which is used by leading CPU/GPU/HyperScaler companies for pre-Silicon software validation of their SOC's.
You will develop new algorithms and optimizations for QoR (Quality of Results) and performance for the Protium Timing flow working with a small team of engineers to develop our next generation FPGA based verification platform.
Responsibilities:
Position Requirements/Qualifications:
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We're doing work that matters. Help us solve what others can't.
We are looking for an experienced C++ software engineer to join the Protium Software Development Team to develop and enhance the FPGA-Based Prototyping product which is used by leading CPU/GPU/HyperScaler companies for pre-Silicon software validation of their SOC's.
You will develop new algorithms and optimizations for QoR (Quality of Results) and performance for the Protium Timing flow working with a small team of engineers to develop our next generation FPGA based verification platform.
Responsibilities:
- Enhance and support Timing Engine to add new features and extend existing features
- Enhance and support Timing Flow to improve P&R compile time
- The role involves designing, tuning, and innovating timing graph algorithms and flow operating on multi-billion-node timing graphs
- Write Specifications and Unit Tests for your code
Position Requirements/Qualifications:
- BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
- Experience in EDA software development.
- Strong background in SDC constraints and Timing Analysis
- Excellent programming skills in C/C++
- Strong knowledge of Tcl is preferred
- Experience in multi-threaded/ concurrent programming are pluses.
- Prior experience with Emulation or FPGA software development is an added plus.
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We're doing work that matters. Help us solve what others can't.
Skills
FPGA
C++
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