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Post Silicon Validation
Tanisha Systems, Inc.Sunnyvale, CA🇺🇸United StatesPosted 8 Jul 2026
Why This Role Stands Out
This Post Silicon Validation role at Tanisha Systems, Inc. offers a fantastic opportunity to work on cutting-edge ML-Coprocessor and SOC technologies, significantly impacting product development. You'll thrive here if you're a mid-senior engineer eager to expand your skills in validation strategy, infrastructure development, and complex SOC validation. Apply now to join a dynamic team and contribute to innovative solutions.
Quick Overview
Work Type
On Site
Level
Mid Senior
Job Description
Job description:-
If you are interested this role please share your Updated resume.
Role: Post Silicon Validation
Location: Sunnyvale CA (Onsite)
Job Type: Fulltime
Validate ML-Coprocessor, display SOC, Mixed Signal SOC, and IP.
• Define validation strategy and test plans for new IP blocks, aligning with RTL, architecture, FW.
• Develop silicon validation infrastructure and coding C/C++ and Python for emulation (Zebu), FPGA (HAPS), and first silicon platforms. Identify risks and develop mitigation strategies.
• Execute bring-up/debug, workload enablement, and ML accelerator SW stack validation.
• Perform performance and power characterization under real ML workloads.
• Create automated data collection flows and convert large datasets into executive summaries.
• Track test coverage, document bugs, drive cross-functional debug, and verify silicon fixes.
• Participate in design reviews and provide recommendations to strengthen validation coverage.
• Collaborate with factory test teams to align validation and production characterization strategies.
If you are interested this role please share your Updated resume.
Role: Post Silicon Validation
Location: Sunnyvale CA (Onsite)
Job Type: Fulltime
Validate ML-Coprocessor, display SOC, Mixed Signal SOC, and IP.
• Define validation strategy and test plans for new IP blocks, aligning with RTL, architecture, FW.
• Develop silicon validation infrastructure and coding C/C++ and Python for emulation (Zebu), FPGA (HAPS), and first silicon platforms. Identify risks and develop mitigation strategies.
• Execute bring-up/debug, workload enablement, and ML accelerator SW stack validation.
• Perform performance and power characterization under real ML workloads.
• Create automated data collection flows and convert large datasets into executive summaries.
• Track test coverage, document bugs, drive cross-functional debug, and verify silicon fixes.
• Participate in design reviews and provide recommendations to strengthen validation coverage.
• Collaborate with factory test teams to align validation and production characterization strategies.
Skills
FPGA
C++
Python
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