Design Verification Engineer (Onsite in San Jose, CA ) Local Only

We are seeking a highly motivated Design Verification Engineer to join our Interface IP DV team. In this role, you will collaborate closely with architects, designers, and external vendors to ensure that architecture requirements are fully implemented across IP subsystems and interfaces. You will play a critical role in validating functional correctness and performance across the complete hardware-software stack.

This position requires strong technical expertise, creativity, and the ability to solve complex verification challenges in a fast-paced semiconductor environment.

Key Responsibilities

• Own end-to-end verification activities for one or more IP subsystems, including:
• PCIe
• Ethernet
• CPU subsystems (ARC/ARM)
• Low-power peripherals
• Sensors
• Understand vendor IP configurations and manage technical handshakes with internal IP teams.
• Develop and maintain robust UVM/SystemVerilog-based verification environments to ensure:
• Functional correctness
• Performance validation
• Compliance with IP specifications
• Collaborate with Integration and SoC DV teams to validate seamless interoperability of external IPs within the broader chip architecture.
• Drive coverage closure and verification sign-off by:
• Defining verification metrics
• Analyzing coverage gaps
• Ensuring comprehensive validation across corner cases and stress scenarios

Required Skills & Qualifications

• Strong expertise in SystemVerilog and UVM
• Experience with IP/Sub-system verification in complex SoC environments
• Solid understanding of protocols such as PCIe and Ethernet
• Experience working with ARM/ARC-based CPU subsystems
• Knowledge of coverage-driven verification methodologies
• Strong debugging and problem-solving skills
• Excellent collaboration and communication abilities