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Verification Consultant

Technical LinkAustin, TX🇺🇸United StatesPosted 22 Jul 2026

Why This Role Stands Out

This on-site Verification Consultant role offers a competitive hourly rate and the chance to own critical gate-level simulations and contribute to high-performance computing verification. You'll thrive here if you possess UVM/System Verilog and Gate-Level Simulation Ownership experience, looking to make a significant impact within a reputable technical environment. Apply now to leverage your expertise and expand your skills in this dynamic opportunity.

Quick Overview

Salary
€93/hr
Work Type
On Site
Level
Mid Senior

Job Description

6 months

Start Date – August 31

Austin, TX (onsite) – San Jose can be an option for perfect candidate

Pay Rate - $93/hr

Must Be W-2

Must Have:

Gate Level Simulation Ownership is most important….needs to have this experience.

UVM/System Verilog Experience

High performance computing background would be a huge +…someone from AMD, Qualcomm, etc

AXI/CHI protocols

 

Position Details

Vertical Description

Technical
As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role.

Key responsibilities include:
• Owning Gate-level simulations TB bringup
• Owning power-aware verification with UPF
• Collaborating with Physical design teams, running and debugging gate-level simulations
• Working with SoC team to debug functional fails during IP bringup and feature execution
• Creating test benches, verification environments, stimulus, tests
• Collaborating with designers to verify the correctness of a design feature, and resolve fails
• Developing assertions, checkers, covergroups, Systemverilog constraints
• Debugging and root causing functional fails from regressions
• Analyzing code and functional coverage results, performing gap analysis
• Helping with Silicon bringup and root causing fails

Requirements

• PhD/MS/BS in Electrical or Computer Engineering • 12+ years industry experience in a design verification role • Expert hands-on coding skills in Testbench, Stimulus, checkers development, coverage closure. • Experience with System Verilog, UVM or equivalent • Atleast 5+yrs of experience with Gate-Level simulations • Knowledge of ARM protocols or equivalent protocols – CHI, AXI, ACElite, APB • Experience with Git version control, Unix/Perl/Python scripting • Good written and verbal communication skills

Skills

Git
Perl
Python
Verilog

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