DevOps Engineer – Semiconductor EDA Tools & Automation with Security Clearance

Change the world. Love your job. Mission 
Empower TI to excel in semiconductor design and manufacturing by architecting, automating, and optimizing secure, high-performance environments for Electronic Design Automation (EDA) workloads. You will enable R&D and engineering teams to innovate faster by delivering scalable DevOps solutions that streamline the deployment and operation of EDA tools—including Cadence PSPICE, Artisan (TI internal EDA flow), PDKs (process development kits) and others—across cloud and hybrid infrastructure.

As a DevOps Engineer, you’ll be instrumental in building and automating workflows for compute-intensive EDA applications in a secure, compliant, and highly available environment. Your work will directly impact TI’s ability to deliver advanced semiconductor products to customers by ensuring seamless integration, operation, and optimization of industry-leading EDA toolchains.

You will:  • Design, automate, and manage DevOps pipelines for deploying and operating semiconductor EDA tools (Cadence PSPICE, Artisan, etc.) on-prem and in the cloud.  • Work closely with EDA tool vendors, TI EDA teams, and PDK teams while responding to customer inquiries.  • Build and maintain scalable infrastructure for simulation, verification, and design workloads, leveraging LSF or Slurm job schedulers.  • Develop and manage infrastructure-as-code solutions to automate provisioning, configuration, and scaling of EDA environments.  • Collaborate with engineering, IT and security teams to ensure robust cybersecurity controls and compliance for sensitive design data.  • Optimize compute, storage, and network resources to deliver fast, reliable access to EDA tools for global R&D teams.  • Troubleshoot, monitor, and enhance performance of EDA workloads and DevOps pipelines, driving continuous improvement.

Core Responsibilities:  • Deploy, configure, and automate EDA tools (Cadence PSPICE, Artisan, etc.) in hybrid and cloud environments.  • Design and manage high-performance, secure infrastructure for EDA workloads using LSF or Slurm job schedulers.  • Implement and maintain CI/CD pipelines for EDA application updates, test automation, and environment provisioning.  • Apply best practices for security, compliance, and operational reliability in semiconductor design environments.  • Provide technical guidance to engineers and researchers on DevOps, automation, and EDA workload optimization.

Qualifications
⁠⁠⁠⁠⁠⁠⁠Minimum Qualifications (Required):  • Current U.S. DoD Secret security clearance or higher (non-negotiable)  • Bachelor’s degree in Computer Science, Engineering, or related field  • 3+ years hands-on experience automating and deploying semiconductor EDA tools (e.g., Cadence Allegro, PSPICE, or Artisan; Altium Designer; AutoCAD; SIMetrix) in enterprise environments

Preferred Qualifications:  • Strong background in DevOps practices, infrastructure-as-code (Terraform, CloudFormation, or similar), and automation scripting (Python, Bash, etc.) • Experience with LSF or Slurm job schedulers for high-performance compute workloads  • Experience with cloud platforms (AWS, Azure, or GCP) and hybrid infrastructure  • Experience supporting semiconductor design, simulation, or verification workloads at scale  • Experience with EDA license server deployment and management  • Knowledge of network and storage architecture for high-throughput environments  • Cloud certifications (e.g., AWS, Azure)  • Familiarity with regulatory and data security standards in the semiconductor industry  • Solid Linux administration skills  • Strong analytical and troubleshooting skills  • Excellent communication and collaboration ability