PCIe Verification Engineer

Job Title : PCIe Verification Engineer

Job Location - Address : San Francisco, California, United States - remote

Client Interview : No

Study Level : Bachelor's Degree

Skill Cluster : 423 - DA-Platfrm Pega AccelQ.

Primary Skill : Simulator, C++

Experience : 12+ years

Job Description :

• PCIe Protocol IP Verification Expert: Consulting & Turnkey projects Virtusa Semiconductor BU is looking for seasoned professionals in the ASIC Verification domain.
• Virtusa is invested in AI/HPC [High Performance Computing] customers who are emphasizing on shift left pre-silicon approaches.
• IP integration and interoperability with multiple Vendor PHY is becoming important to be validated for SOC Integration & Bring Up.
• Complex System Level Environment targeting latest protocol interfaces & switches for scale up and scale out data centers Virtusa is looking for PCIe protocol experts to integrate the 3rd Party IP s [Synopsys, Cadence, Qualitas & other Vendors] with Rambus PCIe Gen6 controller/PHY & validate with complete regression suite.

Job Description

• Application or Product Engineering background with minimum 5 to 10 years of experience is required in SOC/IP Verification.
• Deep Knowledge of FW/SW/Driver with linkup/enumeration/device ID/interoperability of PCIe IP [Gen1 to Gen6/7] plus PHY in subsystem or SOC level . Skills Requirements Digital design with system verilog RTL coding at IP/System Integration level.
• Experience with one of the simulators like Questa , VCS & Xelium. Ability to put together top level wrapper with PCIe DUT at sub system level with PHY [Root Complex & End Point Device], clocks/reset & glue logic required.
• Ability to understand the complex scripted simulation regression environment with UVM & C/C++ testbenches, modify to enhance the test suit and do the functional verification. Knowledge of Python, C/Perl scripting is required.
• Expertise in debugging the complex PCIe bring up scenarios like LTSSM state machines for link up & enumeration steps.
• Understand the configurations of all Generations of PCIe combinations for debugging the failures.