Power Analysis Engineer

Job Role: Power Analysis Engineer
Location: Sunnyvale CA or Austin TX

Full time

Job Description: Low Power Design Engineer — Reality Labs
Experience: 4+ years in VLSI / Semiconductor Design
About the Role
We are looking for a Low Power Design Engineer to join the Silicon SOC team at Reality Labs. The role focuses on power analysis, RTL power estimation, and power optimization for next-generation wearable and AR/VR SoC designs. You will work on power-critical flows that directly impact battery life and thermal performance of our products.
Mandatory Requirements
1. Power Analysis Tool Experience (MUST HAVE)
At least 1 year of most recent experience in one of the following:
Priority Tool Vendor
Preferred Synopsys PrimePower / PTPX Synopsys
Acceptable Ansys PowerArtist Ansys
Acceptable Cadence Voltus Cadence
⚠️ Candidates with PrimePower/PTPX experience will be given first priority.
2. RTL Power Estimation (MUST HAVE — at least one)
3. Power Replay Methodology
4. Minimum Experience
Priority Criteria
🟢 P1 — Interview immediately PrimePower/PTPX + PP-RTL/RTL-A + Power Replay (all three)
🟡 P2 — Strong consider PrimePower/PTPX + at least one of PP-RTL or Power Replay
🟠 P3 — Review carefully PowerArtist or Voltus (no PrimePower) + 5+ yrs low-power experience
🔴 P4 — Pass No power analysis tool experience, or only PD/STA/verification background
Perform gate-level and RTL-level power analysis using PrimePower/PTPX or equivalent tools
Hands on year of most recent experience must be on power analysis tools (PrimePower preferred)
4+ years total in VLSI / semiconductor low-power design
Experience with simulation or emulation-based power replay analysis
Cadence Joules (acceptable equivalent)
Synopsys PrimePower-RTL (PP-RTL) / RTL Architect (RTL-A) (preferred)