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Formal Verification Engineer

Vings TechnologiesSan Jose, CA🇺🇸United StatesPosted 4 Sept 2026

Why This Role Stands Out

Elevate your career as a Formal Verification Engineer at Vings Technologies, where you'll leverage advanced techniques to ensure cutting-edge design correctness and contribute to impactful projects. This hybrid role offers a fantastic opportunity for experienced engineers skilled in SVA and formal verification tools to thrive within a collaborative environment and make a significant difference. Apply today to join a forward-thinking company and expand your expertise.

Quick Overview

Seniority
Mid Senior
Work mode
Hybrid
Location
San Jose, CA, United States
Posted
22 hours ago
Verilog

Job Description

Role Summary
We are looking for formal verification experts to ensure design correctness using mathematical verification techniques and advanced formal tools.

Key Responsibilities
·       Develop formal verification strategies and methodologies
·       Write System Verilog Assertions (SVA)
·       Perform property checking, equivalence checking, and CDC/RDC analysis
·       Identify corner cases missed in simulation
·       Collaborate with RTL teams for design improvements
 
Required Skills:
·       Strong knowledge of formal verification tools (Jasper, VC Formal, etc.)
·       Expertise in SVA and property specification
·       Solid understanding of digital design and logic reasoning
 
Good to Have:
·       Experience in low-power/CDC verification
·       Exposure to security verification
 

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