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FPGA Verification Engineer

Inherent TechnologiesSanta Clara, CA🇺🇸United StatesPosted Sep 21, 2026

Why This Role Stands Out

This role offers an exciting opportunity to advance your FPGA verification expertise within a reputable company, tackling complex challenges and contributing to cutting-edge technology. You'll thrive here if you possess strong System Verilog and UVM skills, a passion for problem-solving, and a desire to collaborate with a talented engineering team. Apply today to leverage your mid-senior level experience and grow your career in Santa Clara.

Quick Overview

Seniority
Mid Senior
Work mode
On Site
Location
Santa Clara, CA, United States
Posted
Yesterday
FPGAVHDLVerilog

Job Description

Job Title: FPGA Verification Engineer
Location: Santa Clara, CA-Onsite 100%, Day 1 Mon-Fri
Duration: 12+ Months


Mandatory Areas
Must Have Skills FPGA Verification Engineer
Skill 1 8 + Years of in FPGA
Skill 2 5 +Years of Exp in UVM
Skill 2 5 +Years of Exp in System Verlilog


Job Description:
Strong understanding of FPGA design principles and architectures.
Proficiency in System Verilog and UVM verification methodology.
Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS).
Knowledge of code coverage and functional coverage analysis.
Excellent debugging and problem-solving skills.
Strong communication and collaboration skills.
Requirements:
Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field.
Experience in FPGA verification.
Experience with scripting languages (e.g., Python, Perl).
Familiarity with hardware description languages (e.g., VHDL, Verilog).


Rohit Chauhan

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