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ASIC Emulation Engineer

R Cube Creative Consulting IncSan Jose, CA🇺🇸United StatesPosted 4 Aug 2026

Why This Role Stands Out

This hybrid role offers a fantastic opportunity to advance your ASIC emulation expertise on cutting-edge projects, collaborating with a talented team to accelerate pre-silicon validation and silicon bring-up. You'll thrive here if you possess strong experience with emulation platforms and high-speed interfaces, and are eager to contribute to innovative SoC development.

Quick Overview

Seniority
Mid Senior
Work mode
Hybrid
Location
San Jose, CA, United States
Posted
3 weeks ago
FPGAVerilog

Job Description

  • Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and
    memory technologies such as LPDDR and HBM
    Set up and maintain Siemens Veloce emulation and prototyping platforms
    Adapt SoC designs for Emulation and Prototyping
    Develop and debug emulation testbenches and system-level environments
    Support pre-silicon validation, power/performance analysis, and early software
    bring-up. Participate in silicon bring-up and validation.
    Collaborate with design and verification teams to isolate design issues and accelerate debug.
    Optimize performance of the emulation workloads and reduce turnaround time.
    Work with firmware/software teams to enable use of emulators for OS and driver testing.

    5 to 10 years of experience

    • BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience.
    • Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based
    • prototyping systems (proFPGA, HAPS, or Protium)
    • Experience with emulating high speed I/O interfaces such as PCIe and UCIe and
    • memory technologies such as LPDDR and HBM
    • Solid understanding of digital design, RTL (Verilog/SystemVerilog), and SoC architecture.
    • Proficiency in hardware debug tools, waveform viewers, and logic analyzers
    • Scripting skills (e.g., Python, Tcl, Perl) for automation and infrastructure development.
    • Familiarity with UVM, simulation, and testbench environments. SystemVerilog and
    • UVM-based verification experience a plus
    • Hands-on software development experience with C/C++ is a plus

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