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Sr. Design Verification Engineer

GTSS IncSan Jose, CA🇺🇸United StatesPosted 20 Jul 2026

Why This Role Stands Out

This role offers significant opportunities to hone your expertise in complex SoC/IP verification, contributing to cutting-edge projects within a reputable company. You'll thrive here if you possess strong SystemVerilog and C/C++ skills, enjoy a full verification cycle from test planning to coverage closure, and are eager to make a tangible impact. Apply now to advance your engineering career in San Jose!

Quick Overview

Work Type
On Site
Level
Mid Senior

Job Description

Role: Senior Design Verification Engineer 
Location: San Jose, CA (Onsite)
Experience: 7+ Years 

What candidate will Be Doing: 

  • Strong expertise along with complex SoC/IP debug is a must
  • At-least 5+ years of experience in System Verilog HVL and C/C++.
  • AMBA AXI bus along-with ARM or C based processor
  • Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench,
  • stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure. 

What we are looking for: 

  • Low Power Verification in UPF/net-list Simulation good to have
  • Make/Perl/Python
  • Ensure customer satisfaction.
  • Reporting to customers on daily or weekly progress effectively 

Skills

Verilog

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