Quick Overview
Seniority
Mid Senior
Work mode
Hybrid
Location
Santa Clarita, CA, United States
Posted
3 days ago
Verilog
Job Description
RTL Verification Engineer
- System Verilog, UVM
- Good knowledge in AMBA,AX4,AHB
- IP/SS/SOC verification experience
- Test Env, test case development
- Regression debug, coverage analysis
- Good knowledge in One of the High speed IF protocol like PCIe6, DDR5, Ethernet or USB3
- Experience in Synopsys/Cadance Tools usage
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