Technology

Software Engineer

Esvee Technologies IncAustin, TX🇺🇸United StatesPosted 6 Aug 2026

Quick Overview

Work Type

Hybrid

Level

Mid Senior

Digital design with system verilog RTL coding from Synthesis point of view..
Experience with emulator ZeBu, Palladium & Veloce.
FPGA Pro typing experience with HAPS, Protium & ProFPGA is plus.
Ability to put together emulation top level wrapper with DUT/System Level, clocks/reset & FPGA partitioning/Place & Route timing closure for successful model build.
Knowledge of Python, C/Perl scripting is a must.
Expertise in HW assisted Verification Test Bench environment : UVM, C++/System C is desired.
Experience integrating and bringing up PCIe Gen6 Protocol Transactor Integration with QeMu is required.
Kernel boot, Linux Boot sequences knowledge & debug is must.

FPGA

C++

Perl

Python

Verilog