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Design Verification Engineer

E-Solutions, Inc.San Jose, CA🇺🇸United StatesPosted 19 Aug 2026

Why This Role Stands Out

This Design Verification Engineer role at E-Solutions, Inc. offers a fantastic opportunity to work on cutting-edge IP blocks within complex SoC environments, fostering significant career growth and skill development. You'll thrive here if you're a mid-senior engineer eager to contribute to a reputable company and collaborate within a dynamic engineering team. Apply to be part of innovative projects and advance your expertise.

Quick Overview

Work Type
On Site
Level
Mid Senior

Job Description

Position: Design Verification Engineer
Type/Duration: Full time//Permanent
Location: San Jose, CA (5 Days onsite in a week)

Summary:

We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Key Responsibilities:

  • Develop and maintain UVM-based verification environments
  • Create test plans, testcases, and coverage models
  • Perform functional verification of RTL designs
  • Debug RTL and testbench issues
  • Drive coverage closure (functional + code)

Required Skills:

  • Strong hands-on with SystemVerilog and UVM
  • Experience in block-level verification
  • Good understanding of digital design fundamentals
  • Experience with debug tools (Verdi, DVE, etc.)

Good to Have:

Exposure to low-power verification (UPF)

Experience with AMBA protocols (AXI/AHB/APB)


Design Verification Engineer1design,Verification,UVM,Verilog,RTLN/AFull TimeUnited States

Skills

Verilog

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